Deposition of silicon dioxide (SiO2) is a critical step of integrated circuit manufacturing; hence it is monitored during the manufacturing process at a grid of points defined on the wafer area. Since collecting thickness measurements is expensive, it is a compelling issue to investigate how a sub grid can be identified. A strategy based on spatial prediction and simulating annealing is proposed to tackle the problem which proved to be effective when applied to a real process. A diagnostic device for monitoring the deposition process is also discussed which can be usefully adopted in the day-to-day activity by practitioners acting in process control of a microelectronics fab.
- Simulated annealing
- Spatial sampling
- Statistics for microelectronics